C++ supported atomic thread fences, that is fences guaranteeing properties for thread that use std::atomic<>
operations, with the function atomic_thread_fence
. It takes a memory order parameter to adjust the "strength" of the fence.
I understand that fences are useful when not all atomic operations are done with a "strong" order:
- when not all atomic reads (1) in a thread are acquire operations, you may find a use for an acquire fence;
- when not all atomic modifications (1) in a thread are release operations, you may find a use for a release fence.
(1) that includes RMW operations
So the usefulness of all these (acquire, release and acq_rel fences) is obvious: they allow threads that use atomic operations weaker than acq/rel (respectively) to synchronize properly.
But I don't understand where memory_order_seq_cst
could be specifically needed as a fence:
What's the implication of using weaker than
memory_order_seq_cst
atomic operations and amemory_order_seq_cst
fence?What would specifically be guaranteed (in term of possible ordering of atomic operations) by a
memory_order_seq_cst
fence that wouldn't be guaranteed bymemory_order_acq_rel
?
atomic_thread_fence
should also affect regular (i.e. not throughatomic<>
) read and writes. – Pericarp