Can anyone point to benchmark results comparing performance of C11/C++11 code using relaxed atomic operations (particularly memory_order_release and memory_order_acquire, but also memory_order_cons...

I took the example about std::memory_order_seq_cst from: http://en.cppreference.com/w/cpp/atomic/memory_order #include <thread> #include <atomic> #include <cassert> std::atomic&...

cppreference.com provides this note about std::atomic_thread_fence (emphasis mine): atomic_thread_fence imposes stronger synchronization constraints than an atomic store operation with the same ...

In his great book 'C++ Concurrency in Action' Anthony Williams writes the following (page 309): For example, on x86 and x86-64 architectures, atomic load operations are always the same, whether...

I've found questions (like this one) asking what [[carries_dependency]] does, and that's not what I'm asking here. I want to know when you shouldn't use it, because the answers I've read all make ...

The main reason for using atomics over mutexes, is that mutexes are expensive but with the default memory model for atomics being memory_order_seq_cst, isn't this just as expensive? Question: Can...

After seeing Herb Sutters excellent talk about "atomic weapons" I got a bit confused about the Relaxed Atomics examples. I took with me that an atomic in the C++ Memory Model (SC-DRF = Sequentiall...

I'm not an ARM expert but won't those stores and loads be subjected to reordering at least on some ARM architectures? atomic<int> atomic_var; int nonAtomic_var; int nonAtomic_var2; voi...

I'm writing some lock-free code, and I came up with an interesting pattern, but I'm not sure if it will behave as expected under relaxed memory ordering. The simplest way to explain it is using an...

-Thread 1- y.store (20, memory_order_release); x.store (10, memory_order_release); -Thread 2- if (x.load(memory_order_acquire) == 10) { assert (y.load(memory_order_acquire) == 20); y.store (10...

The phrase "strongly happens before" is used several times in the C++ draft standard. For example: Termination [basic.start.term]/5 If the completion of the initialization of an object w...

I'm trying to understand these sections under the heading Release-Acquire ordering https://en.cppreference.com/w/cpp/atomic/memory_order They say regarding atomic load and stores: If an atomic ...

C++20 includes specializations for atomic<float> and atomic<double>. Can anyone here explain for what practical purpose this should be good for? The only purpose I can imagine is when I...

Thread A runs x.store(1, std::memory_order_release) first, then thread B runs x.load(std::memory_order_acquire). x in thread B is not guaranteed to read 1 stored by A. If I use memory_order_seq_c...

This could be a language neutral question, but in practice I'm interested with the C++ case: how are multithread programs written in C++ versions that support MT programming, that is modern C++ wit...

I have written a simple 'envelope' class to make sure I understand the C++11 atomic semantics correctly. I have a header and a payload, where the writer clears the header, fills in the payload, the...

Suppose I have 2 threads: int value = 0; std::atomic<bool> ready = false; thread 1: value = 1 ready = true; thread 2: while (!ready); std::cout << value; Is this program able to ou...

Does volatile sig_atomic_t give any memory order guarantees? E.g. if I need to just load/store an integer is it ok to use? E.g. here: volatile sig_atomic_t x = 0; ... void f() { std::thread t([&...

Consider the following code: struct payload { std::atomic< int > value; }; std::atomic< payload* > pointer( nullptr ); void thread_a() { payload* p = new payload(); p->value.st...

If I lock a std::mutex will I always get a memory fence? I am unsure if it implies or enforces you to get the fence. Update: Found this reference following up on RMF's comments. Multithreaded pr...

When reading about consistency models (namely the x86 TSO), authors in general resort to models where there are a bunch of CPUs, their associated store buffers and their private caches. If my unde...

I'm checking how the compiler emits instructions for multi-core memory barriers on x86_64. The below code is the one I'm testing using gcc_x86_64_8.3. std::atomic<bool> flag {false}; int any...

The current draft of the C++ standard (march 2019) has the following paragraph ([basic.types] p.4) (emphasis mine): The object representation of an object of type T is the sequence of N unsigned...

Consider the diagrammed data cache architecture. (ASCII art follows.) -------------------------------------- | CPU core A | CPU core B | | |------------|------------| Devices | | Cache A1 | Ca...

I see that g++ generates a simple mov for x.load() and mov+mfence for x.store(y). Consider this classic example: #include<atomic> #include<thread> std::atomic<bool> x,y; bool r1...