I am trying to find out what an x86 processor does when it encounters a store conditional instruction. For instance does it stall the front end of the pipeline and wait for the ROB buffer to become...

I found a couple of places online which state that CLREX "must" be called whenever an interrupt routine is entered, which I don't understand. The docs for CLREX state (added the numbering...

In the Linux kernel, arch_spin_lock() is implemented as follows: static inline void arch_spin_lock(arch_spinlock_t *lock) { unsigned int tmp; arch_spinlock_t lockval, newval; asm volatile( /*...

Under an x86 processor I am not sure of the difference between compare-and-swap atomic operation and Load-link/store-conditional operation. Is the latter safer than the former? Is it the case that ...

I'm working on the next release of my lock-free data structure library, using LL/SC on ARM. For my use-case of LL/SC, I need to use it with a single STR between the LDREX and STREX. (Rather than us...