Like many others, I've bought myself a new Ryzen CPU. I need to use Anaconda Python for my PhD (together with Tensorflow etc). Since Anaconda now comes pre-packaged with MKL which is slow on AMD CP...

I know that Numpy can use different backends like OpenBLAS or MKL. I have also read that MKL is heavily optimized for Intel, so usually people suggest to use OpenBLAS on AMD, right? I use the follo...

I have an AMD cpu and I'm trying to run some code that uses Intel-MKL. The code is significantly slower than I expected. When you have an AMD CPU, can you speed up code that uses the Intel-MKL? How...

I have the following C++17 code that I compile with VS 2019 (version 16.8.6) in x64 mode: struct __declspec(align(16)) Vec2f { float v[2]; }; struct __declspec(align(16)) Vec4f { float v[4]; }; st...

Is there any particular advantage with 8 way set cache associativity that I fail to see?

How is the Write-Combine buffer physically hooked up? I have seen block diagrams illustrating a number of variants: Between L1 and Memory controller Between CPU's store buffer and Memory controll...

Modern Intel and AMD chips have large store buffers to buffer stores before commit to the L1 cache. Conceptually, these entries hold the store data and store address. For the address part, do thes...

When I run this little assembly program on my Ryzen 9 3900X: _start: xor rax, rax xor rcx, rcx loop0: add rax, 1 mov rdx, rax and rdx, 1 add rcx, rdx cmp rcx, 1000000000 jne loop0 It compl...

On Intel processors, x87 trigonometric instructions such as FSIN have limited accuracy due to the use of a 66-bit approximation of pi even though the computation itself is otherwise accurate to the...

Has there ever been a case of an instruction added to an x86 CPU after release? That is, an instruction that didn't exist/work out of the box CPU, but could work on the same CPU sample after ...

I wrote program that multiplies arr1*arr2 and save result to arr3. Pseudocode: arr3[i]=arr1[i]*arr2[i] And I want to use AVX instructions. I have assembler code for m128 and m256 instructions (...

I've installed Intel Vtune Analyzer 9 to get call-graph and counter-monitor data from a win32 application on a Windows 7 PC with AMD Turion X2 TL-58 processor but it gives an error saying :"The CPU...

I keep getting the error noted above when I try to run a virtual device. My CPU does support virtualisation and it is enabled. I have ran a virtual device on eclipse before but, for some reason,...

I just can't manage to start them. I have read several threads here. I need more guides to try. I've tried genymotion, Visual Studio. I want to code in C#. My processor is the Ryzen 3700x. My error...

When I look at diagrams and overviews of recent processors[1], I never see mention of the MMX registers MM0 - MM7. But from the specs, it seems like they still exist. Can one depend on them being p...

Reading the documentation between Intel and AMD and looking at code makes it difficult at times to understand how to create a proper Task State Segment (TSS) that has no IO port bitmap (IOPB). Ther...

I have read through Intel's Software Development Guide's (vol 1-3). Without doing a doing a similar read through AMD's Programming Guides (vol 1-5), I am wondering what aspects of Intel and AMD's ...

The documnation for PREFETCHT2, which is prefetch with T2 hint, says (emphasis mine): T0 (temporal data)—prefetch data into all levels of the cache hierarchy. T1 (temporal data with respect t...

The C language was used to write Unix to achieve portability—the same C language program compiled using different compilers produces different machine instructions. How come the Windows OS is able ...

In recent Intel ISA documents the lfence instruction has been defined as serializing the instruction stream (preventing out-of-order execution across it). In particular, the description of the inst...

I'm trying to learn x86-64's new AVX-512 instructions, but neither of my computers have support for them. I tried using various disassemblers (from Visual Studio to online ones: 1, 2) to see ...

Can anyone confirm that for example Intel i3 CPU has 2 physical cores and 4 logical cores, so if I set Process affinity to Core #0 so that means I set on first physical cores 1 logical core, but if...

On Intel and AMD x86_64 processors, SIMD vectorized registers have specific fused-multiply-add capabilities, but general-purpose (scalar, integer) registers don't - you basically need to multiply, ...

I have learned about different cache mapping techniques like direct mapping and fully associative or set associative mapping, and the trade-offs between those. (Wikipedia) But I am curious which on...

Why did Meltdown and Spectre bugs go undiscovered for so long? Nearly 20 years these bugs have been present in the CPU's why wasn't this discovered sooner given the serious implications for all c...