Do non-temporal stores (such as movnti), to the same cache line, issued by the same thread, reach the memory in program order? So that for a system with NVRAM (like Intel Cascade Lake processor wit...

SFENCE prevents NT stores from committing from the store buffer ahead of SFENCE itself. NT store data enters an LFB directly from the store buffer. Therefore SFENCE can only guarantees the ordering...

When using persistent memory like Intel optane DCPMM, is it possible to see partial result after reboot if system crash(power outage) in execution of movnt instruction? For: 4 or 8 byte movnti whi...

Commonly, cacheline is 64B but atomicity of non-volatile memory is 8B. For example: x[1]=100; x[2]=100; clflush(x); x is cacheline aligned, and is initially set to 0. System crashs in clflush(); I...

I am trying to use some of the uncore hardware counters, such as: skx_unc_imc0-5::UNC_M_WPQ_INSERTS. It's supposed to count the number of allocations into the Write Pending Queue. The machine has 2...

I am trying to find configuration or memory access pattern for Intel's clwb instruction that would not invalidate cache line. I am testing on Intel Xeon Gold 5218 processor with NVDIMMs. Linux vers...

Is anyone aware of any shortcomings in trying to use the Intel Optane DC Memory (DCPMM) in App Direct Mode (that is as non-volatile memory) to write or read to/from it using Write Through (WT) or U...

I recently learned about the row hammer attack. In order to perform this attack the programmer needs to flush the complete cache hierarchy of a CPU for a specific number of addresses. My question ...