I want to create a wrapper around the x86 instructions PDEP (Parallel Bit Deposit) and PEXT (Parallel Bit Extract). On architectures where these aren't available (and the corresponding intrinsics a...

From here, I learned that the support of AVX doesn't imply the support of BMI1. So how about AVX2: Do all CPUs that support AVX2 also support BMI2? Further, does the support of AVX2 imply the suppo...

I am looking for compiler flags of GCC/CLANG to generate BEXTR instruction. template <auto uSTART, auto uLENGTH, typename Tunsigned> constexpr Tunsigned bit_extract(Tunsigned uInput) { retur...

I watched a youtube video on the Top 10 Craziest Assembly Language Instructions and some of these instructions have no obvious application to me. What's the point of something like PEXT, which take...

The documentation for the parallel deposit instruction (PDEP) in Intel's Bit Manipulation Instruction Set 2 (BMI2) describes the following serial implementation for the instruction (C-like pseudoco...

The Haswell architectures comes up with several new instructions. One of them is PEXT (parallel bits extract) whose functionality is explained by this image (source here): It takes a value r2 an...

It it safe to assume that x64 builds can use TZCNT without checking its support through cpu flags?

I was inspired by this link https://www.sigarch.org/simd-instructions-considered-harmful/ to look into how AVX512 performs. My idea was that the clean up loop after the loop could be removed using ...

In one of my applications, I need to efficiently de-interleave bits in a long stream of data. Ideally, I would like to use the BMI2 pext_u32() and/or pext_u64() x86_64 intrinsic instructions when a...

I have some code that relies on AVX. In the same code base I also use TZCNT. The latter is part of BMI1. I know I can test for this instruction using CPUID, but I'm lazy so I did not actually imple...

I'm a bit confused about both instructions. First let's discard the special case when the scanned value is 0 and the undefined/bsr or bitsize/lzcnt result - this difference is clear and not part of...

I was searching on the web to find a proper solution, without much success. So I hope one of you know something about it: Is there any way to detect the "Intel Bit Manipulation Instruction Sets 2" ...

The mulx instruction was introduced with the BMI2 instruction set starting with the Haswell processor. According to Intel's documentation there should be an intrinsic for mulx unsigned __int64 um...