how many instructions can be stored in instruction queue of 8086 microprocessor?

Question

I think,since memory of intel microprocessors is byte organized and size of instruction queue is 4 bytes,the answer would be 4 instructions?

Rentier

Answer 1

The 8086 and 8088 chips have prefetch queues. These stored a number of bytes pre-fetched from the memory "ahead" of the instruction pointer (and code segment). This allows the processor to do something "useful" in what otherwise would have been an idle bus cycles.

The 8088 prefetch queue was four bytes deep. The 8086 queue was six bytes deep.

Again, these do not correspond to a set number of instructions, but a number of bytes.

So the answer to your question is as many as four (or six) (single byte) instructions, or not even one whole instruction (for the longer ones).

BTW: The 8088 had a smaller queue because its small 8 bit bus meant that there were fewer idle cycles available and a bigger queue would have slowed the process down. The 8086 can fill its queue in 3 bus cycles, the 8088 needs four cycles to fill its smaller queue.

Nucleolus

Why would a larger prefetch queue make 8088 slower? It doesn't have to wait for the buffer to fill before decoding an instruction, does it? i.e. a one-byte xchg ax, cx can decode and execute as soon as its fetched, even if it's the only byte in the buffer, right? I'd guess that 8088 didn't benefit as much from a larger queue, so it makes sense to cut it down along with the bus width, though, just to lower the transistor count. – Boyette

No, instructions can be decode right after they are fetched. This issue is bus usage. If too much prefetching is going on, they can interfere with data fetches. The 8086 can fill a six byte queue in as few as 12 clock cycles. The 8088 would take 24 clocks to fill a 6 byte queue, but only 16 clocks for a four byte queue. – Nucleolus

Ok, right, but doesn't data load/store have priority over instruction (pre)fetch? I guess even with that, the next data access would still have to wait for the next slot of not-fully-pipelined memory access if an instruction byte load was in flight. So the buffer actually fills often often enough to make a difference on 8088? – Boyette