I am clock gating some latch and logic in my design. I don't have much experience in synthesis and place & route. What is the proper way to implement clock gating in RTL? Example1: always_co...

Which code is better in writing a RAM? assigning data_out inside always block: module memory( output reg [7:0] data_out, input [7:0] address, input [7:0] data_in, input write_enable, input...

In verilog I have an array of binary values. How do I take the absolute value of the subtracted values ? Verilog code: module aaa(clk); input clk; reg [7:0] a [1:9]; reg [7:0] s [1:9]; alw...

i am unable to get correct output in a text file however simulation in modelsim is quite ok.. but while writing it to text file im getting XX for every input. may be there is some syntax error or s...

I'm working on a simple sign-extender in Verilog for a processor I'm creating for Computer Architecture. Here's what I've got so far: [EDIT: Changed the selection statement slightly] `timescale 1...

May be this question a bit not for StackOverflow, but both compilers and Verilog (which can be considered as programming language) are related to this project. Where can I find a open-source ...