I have read Intel 64 and IA-32 Architectures SDM vol 3A, 9.2 MEMORY ORDERING, but there was one question that kept bothering me. If I first write to a memory address, then send an interprocessor in...

I am trying to write a simple application that can read msr registers, and am running this application from userspace. I have loaded the msr module and given read permissions for everyone to /dev...

First of all, I do not know whether I should be asking this here or in the Electronics StackExchange, so please let me know if you think I should ask it there. I am interested in measuring the ener...

Is there some way to read the x86-64 model-specific registers, specifically IA32_FS_BASE and IA32_GS_BASE, while debugging a program using GDB? Less preferable would be a solution using a dynamic ...

I'm trying to undervolt my CPU on a Intel Skylake machine running Ubuntu 18.04 / kernel 4.18.0-16 in Secure Boot mode and need to read/write MSR 0x150. I have signed and loaded the msr.ko kernel mo...

I am trying to disable hardware prefetching on my machine: CPU family: 6 Model: 78 Model name: Intel(R) Core(TM) i5-6200U CPU @ 2.30GHz I have checked with: gcc -march=native -Q --help=target|grep ...

Every modern high-performance CPU of the x86/x86_64 architecture has some hierarchy of data caches: L1, L2, and sometimes L3 (and L4 in very rare cases), and data loaded from/to main RAM is cached ...

I installed perf on Haswell CPU( Intel Core i7-4790 ). But the "perf list" does not include "stalled-cycles-frontend" nor "stalled-cycles-backend". I checked the http://www.intel.com/content/www/us...

I am getting Error while trying to disable Hardware prefetcher in my Core i7 system. I am following the method as per the link How do I programmatically disable hardware prefetching? In my system ...

I'm trying to use CPUID, but there are some strings attached. According to sandpile.org's CPUID page, CPUID standard functions 0000_0004h and up will only work if the MISC_ENABLE.LCMV flag is set t...