Why doesn't there exists a subi opcode for MIPS?

Question

I am very new to Assembly language. I was reading about MIPS architecture and came to know that you have addi opcode but there is no subi opcode. Why don't we have a subi opcode?

Undercoating

Near-duplicate What is the "relationship" between addi and subi?. Some MIPS assemblers implement subi as a pseudo-instructions. (including the MARS simulator but not SPIM.) – Asseveration

Answer 1

When you create an instruction set, you're bound by some constraints, such as the total number of instructions you can create. The MIPS creators realized that there isn't a need for subi (because you can add a negative number with addi using 2's complement), and they simply made the decision to forego making that instruction. It may have been to conserve the number of instructions, or just simply because it isn't needed.

Fan

Thanks a lot. So they followed there rule, i.e "Less is more." – Undercoating

@JustAnotherProgrammer - that's probably the case. Good luck with MIPS! Patterson and Hennessy is a great book for learning computer architecture (the bible), and the SPIM simulator is a decent tool if you want to practice your MIPS assembly. – Fan

Why is 'sub' needed then? Can't we use 'add' to do any 'sub' operation by taking 2's complement – Singley

@mskd96 Yes, you could perform a sub that way, so it is not strictly necessary. But, unless there is another important operation that would be omitted from the ISA by including sub, it isn't detrimental to include it in the ISA. – Fan

@mskd96 you forgot 1 of Patterson and Hennessy's design principles: "Make the common case fast". sub is much more common than subi with immediates larger than 32767 so that'll why the instruction was introduced, otherwise we can have a complete instruction set with only 1 instruction and also very slow to do common things. "Good design demands good compromises" – Spontaneous

Answer 2

Both addi and addiu take 16-bit signed immediates as operand, so it makes no sense to add separate subi and subiu opcodes.

Repugn

They could easily have added a subi opcode to the assembler that maps to the same hardware instruction. – Weiler

@Bo Any decent MIPS assembler does support subi mnemonic (which emits addi). – Upstream

@Bo Persson: then it wouldn't be an opcode, but a pseudo-instruction :) – Repugn

Just a question: is immediate in addi sign-extended when being added to a register? – Wren

@user35443: yes, also for ADDIU (ADDIU only differs from ADDI in that it does not raise Overflow Exceptions) – Repugn