Why does Hyper-threading get reported as supported on processors without it?

Question

I'm trying to gather system information and noticed the following on an Intel Xeon E5420:

After executing CPUID(EAX=1), EDX[28] is set, indicating Hyper-threading support, despite the fact that the processor is listed on the Intel website as not supporting Hyper-threading (ark.intel.com)

Does anyone have an explanation for this?

Hoist

It's "hyper-threading" just the special case of only one thread. – Pulp

Related: msdn.microsoft.com/en-us/library/hskdteyh.aspx "With the AMD chipset, all multi-core AMD CPUs set bit 28 of the feature information bits to indicate that the chip has more than one core. This is the case even though AMD does not support hyper-threading." But that's for AMD chips. – Heloise

The chart on MSDN also labels bit 28 as "Multithreading"... – Heloise

Answer 1

Here's the definition of that bit according to the Intel Developer's Manual:

Max APIC IDs reserved field is Valid. A value of 0 for HTT indicates there is only a single logical processor in the package and software should assume only a single APIC ID is reserved. A value of 1 for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of addressable IDs for logical processors in this package) is valid for the package.

In chapter 8 of volume 3A of the manual, it describes how one properly detects hardware multi-threading.

Here's a link:

http://download.intel.com/products/processor/manual/325462.pdf

Parisparish

Yes, this does seem to show that the HTT bit has over time come to indicate more than one logical thread per package, whether because of HTT or multiple physical cores. – Hoist

Answer 2

There is a semi-official explanation in an Intel talk https://software.intel.com/en-us/articles/hyper-threading-technology-and-multi-core-processor-detection

Basically after Intel introduced SMT/hyperthreading in the final versions of the Pentium 4, they created the Pentium D, which being multi-core was considered an evolution of the hyperthreading model because a core has more independence from another core than SMT units have relative to each other, and thus multi-core performs better than SMT at the same thread count. So they used the same bit to indicate SMT/hyperthreading or multi-core for that reason, i.e. multi-core was seen as an improved form of hyperthreading. The Intel Xeon E5420 that you ask about is a multi-core processor, so that's why the bit is set.

Of course, once you can have both hyperthreading and multi-core in the same package, it's sometimes necessary to tell them apart, for example because you'd rather schedule a new thread on an unloaded core rather than on the other hyper-threaded half of an already loaded core. So new cpuid bits (or rather leaves) were eventually introduced for the purpose of describing a combined SMT and multi-core topology. The most recent of these newer cpuid features for querying processor topology is the EAX=0xB leaf.

As an aside, you should not use the topology enumeration algorithm given in that old Intel talk for processors made in 2010 and thereafter because it will give incorrect/inflated core counts. Use the updated method given at https://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/ instead. Alas this newer page is much more dry and doesn't for example answer the question that you asked, whereas the old talk does...

Chenille