Is the PADDD instruction actually supported by MMX, even though it's missing from Intel's manual?

Question

I wrote this code in NASM:

PADDD mm0, mm1

And it was assembled with no errors, but this instruction, though it exists in NASM, I couldn't find it in Intel Instructions Manuals, all I found is this:

PADDD xmm1, xmm2/m128

Which takes an xmm register and not an mm register.
This is the opcode of PADDD mm0, mm1: 0FFEC1
And this is the opcode of PADDD xmm0, xmm1: 660FFEC1
So why PADDD mm0, mm1 is missing in Intel's Instructions manuals?

Virginity

I don't know your source, but it exists here. – Ictinus

@BenSteffan I found it here too : en.wikipedia.org/wiki/X86_instruction_listings. But in the manual, it doesn't exist. – Virginity

You seem to be correct. In the latest Intel manual the mmx variant is notably absent. In an older version of the Intel manual from 2005 it is listed. – Aneto

For the record, it's also present in the march 2017 volume 2. – Connubial

Answer 1

This is a simple case of a typo/omission in the current version of Intel's manuals.

On this site, which hosts a copy of the Intel docs (although not necessary the latest Intel docs), the opcode for MMX is present:

Opcode/Instruction    Op/En                64/32 bit Mode Support     CPUID Feature Flag  Description
0F FC /r1            PADDB mm, mm/m64 RM  V/V                        MMX                 Add packed byte integers from mm/m64 and mm.

You will also find it in an older Intel manual from 2005, as well as in the March 2017 version.

Nothing to see here; please move along.

Lamprophyre