Difference between an instruction and a micro-op

Question

What is the difference between a machine instruction and a micro-op? I found a following definition here:

A small, basic instruction, used in series to make up a high-level machine instruction

Here is what I found on Wikipedia

In computer central processing units, micro-operations (also known as a micro-ops or μops) are detailed low-level instructions used in some designs to implement complex machine instructions (sometimes termed macro-instructions in this context)

Am I correct in understanding that micro-op is a processor instruction that executes in a given cycle. Say like and ADD, SUB, MUL, ST, LD. Am I missing something?

Any help is appreciated.

Synecology

Micro-ops are basically a way to turn CISC-instructions into RISC-instruction. For example, most RISCs are exclusively load-store (most instructions only work on registers), while CISCs may be able to operate directly on memory-operands. On modern CISC-microarchitectures, the memory-load/store part of an instruction can be decoupled from the ALU-operation by issuing two micro-instructions. – Willow

@EOF So basically these are machine instructions. It is just not all of them are visible to the programmer. In other words one a programmer can write some assembly instruction, however a compiler will break it down to 2 or 3 instructions. Am I correct? – Synecology

Not quite. I'd look at the difference between an ISA and a micro-architecture to understand this. It's not the compiler that turns machine instructions (defined by the ISA) into micro-instructions, it's the CPU itself. – Willow

@EOF What if we are talking only about RISC architecture? Does micro-op mean the same thing as an instruction or there are exceptions? – Synecology

Answer 1

Quite a few years ago it was discovered that RISC was better than CISC. If you wanted a very high speed processor then you wanted all your instructions to be very simple. This allows them to complete in a short period of time and thus a higher clock speed. So Andrew Tanenbaum predicted that "5 years from now no one will be running x86". That was in the 90s.

So what happened? Isn't the x86 (and thus AMD64, also known as x86_64) the best known CISC instruction set? Well, don't underestimate the ingenuity of the Intel (and AMD) engineers. Realising that if they wanted a higher speed processor (back with one core we were hitting > 4GHz in the late 90s) that they couldn't process their complex instructions in one clock cycle. The solution was to use "micro-ops".

Each micro-op would execute in a single clock cycle and would resemble a RISC type instruction. When the processor encountered the CISC instruction it would decode it into several micro-ops, each of which would last one cycle. Thus they could keep their old cruddy instruction set architecture (for backwards compatibility) and have very high clock speeds.

Astrakhan

So is the definition of micro-ops is only valid for CISC architecture? Can there be micro-ops in a RISC architecture? – Synecology

Well, "micro-op" doesn't have a well defined definition as far as I'm aware. If you were talking about a RISC instruction set and said micro-op then I'd ask if you were meaning the pipeline stages. But typically, no, micro-op is the break down of a CISC instruction to RISC. – Astrakhan

Are you sure that "each micro-op runs in one cycle"? How do you decompose, say, div into micro-ops of one cycle each? – Shortchange

An interesting realization about RISC-vs-CISC is that if you only give the programmer small instructions, then the programmer (or compiler) must be smart enough to compose them into a sensible sequence. But it turns out that the CPU is in a better position to make informed decisions on how to order the instructions, and a lot of performance has been gained by clever instruction reordering that's done by the CPU. So x86 + smart instruction reordering actually results in pretty decent performance. – Shortchange

@KerrekSB: you are right, I should probably edit my answer, I was being a little bit loose in my explanation ... I was thinking of the CISC type instructions, not a long latency RISC type one. – Astrakhan

So "micro-ops" are a new and distinct thing unrelated to the instructions that microcode would consist of? – Witkin

@hippietrail: It is actually highly related. In What is a microcoded instruction?, I made the point that when we say "a microcoded instruction" when talking about x86 optimization, we mean one where the uops (micro-ops, that should be a Greek mu but I'm lazy) come from the microcode sequencer ROM, rather than being hard-wired into the decoder itself. (On Intel, instruction that decode to 1 to 4 uops can be handled by the decoders without having to indirect to the MS-ROM). But they are the same kind of uops that all go through the back-end. – Godderd

@hippietrail: See Agner Fog's microarch guide (agner.org/optimize) to better understand this. Also realworldtech.com/merom (Core 2) and realworldtech.com/sandy-bridge for more about internals. Oh also, realworldtech.com/risc-vs-cisc from 2000 looks at how PPro breaks down instructions into uops, vs. RISCs where most instructions are already simple, and only a few every need to be expanded to send multiple things down the pipeline (aka microcoded). – Godderd

@hippietrail: You could call any multi-uop x86 instruction "microcoded", like you would in RISC terms, but it's useful to use the term "microcoded" to make a different distinction, IMO. – Godderd