how to view memory waveform?

Question

I can't view memory using gtkwave:

    module internal_memory(
        output [31:0] hrdata,
        input mem_enable,
        input [31:0] haddr,
        input [31:0] hwdata,
        input hwrite,
        input hreset,
        input hclk
    );
        reg [31:0] memory [0:1023]; // <-------------- can't find its waveform
        reg [31:0] internal_hrdata;

        always @(posedge hclk, hreset) begin
            if (!hreset) begin
                internal_hrdata <= 32'h0000_0000;
            end
            else begin
                if (mem_enable) begin
                    if (hwrite) begin
                        memory[haddr] <= hwdata;
                    end
                    else begin
                        internal_hrdata <= memory[haddr];
                    end
                end
            end
        end

        assign hrdata = internal_hrdata;

    endmodule

What can you suggest to view the waveform of memory?

Or how to display two-dimensional array in gtkwave or in any .vcd/waveform viewer?

Stotinka

Answer 1

You need to first dump the memory into the VCD file. The 2 simulators I am familiar with require extra simulation options for dumping memories into the VCD; perhaps yours does too.

Miffy

Look in your simulator docs for "VCD", then dump the top level nodes that you're simulating. – Roborant

I'm using icarus verilog. Well, I guess I have to figure out this one. Thanks for the answer anyway. – Stotinka

I had gone through the documentation of Icarus Verilog. Sadly, it didn't helped. – Stotinka

Is it possible to implement a PLI program for dumping memories? – Stotinka

Answer 2

I know this is an old question, but I recently had to view a simulated memory with Icarus/GTKWave for a course final project and wanted to answer this for anyone reading this question. I was able to find the answer on the Icarus Verilog Portability notes (see source).

With Icarus, you need to dump each array word (memory location) you want to look at explicitly:

module top;
   reg [7:0] array [2:0];
   initial begin
     $dumpvars(0, array[0], array[1]);
     ...
   end
endmodule

You can automate dumping all of the cells in an array with a for loop:

module top;
   integer idx; // need integer for loop
   reg [7:0] array [2:0];
   initial begin
     for (idx = 0; idx < 2; idx = idx + 1) $dumpvars(0, array[idx]);
     ...
   end
endmodule

Source: http://iverilog.wikia.com/wiki/Verilog_Portability_Notes (Dumping array words)

Odelet