L1 cache ports in ARM Cortex processors

Question

I did some reseach, but could not find much information.

I'd like to know how many L1 read and L1 write ports ARM embedded processors have and how wide the ports are. Specifically, I am interested in Cortex-A8, Cortex-A9, and Cortext-A15.

My blind guess is that a Cortex-A9 processor has one L1 read port and one L1 write port which are 64 bits wide. My other guess is that it has a single shared read/write port. Any thoughts on that?

Collins

No, you got it wrong. Line buffer is something else and has nothing to do with ports. – Collins

All Cortex-A CPUs use an AXI bus. It is 64bit for 32bit CPUs, so the port size will be at least 64bits. The only definitive answer is the TRM (as others answered). – Emunctory

Answer 1

These processors have separate L1 instruction and data caches. I'm pretty sure all ARM cores' L1 I-cache and D-cache each have 1 read and 1 write port Furber p.81.

L1 Cache is in each core, so for details I'd go to core TRM e.g. Cortex-A9 TRM rather than an MPCore TRM. Ch 7 there tells of 64-bit datapath for each.

Lindsylindy

Thanks for the answer. Do they have one dedicated (exclusive) read and one dedicated write port or one shared read/write ports? Or it even could be two shared read/write ports? BTW, I don't have access to that book, that's why I am asking. Chapter 7 has much information I was looking for. – Collins

Hm, Furber shows separate read ports of I-cache and D-cache but doesn't show write ports. I should find a reference to justify my answer. Patterson-Hennesey p. 530 cite separate cache->mem and mem->cache paths, which makes sense. Cortex-A9 TRM data and instruction prefetch descriptions imply dedicated mem->cache paths. – Lindsylindy

Just one thing to clarify here. I am talking about port(s) between L1 DATA cache and cpu. L1 to L2 connection and L2 to memory connection are subjects of another topic. – Collins

Answer 2

Afaik you should check the AXI capabilities of each processors.

For example page for Cortex-A9 contains a detailed table for AXI master interface attributes and states:

The Cortex-A9 MPCore L2 interface can have two 64-bit wide AXI bus masters.

Page for Cortex-A15 contains less information, stating:

The processor implements an AMBA 4 AXI Coherency Extensions (ACE) master interface and an AMBA 3 AXI Accelerator Coherency Port (ACP) slave interface. Both the ACE and ACP support a hardware configurable 64-bit or 128-bit data width.

There also exists a similar page or Cortex-A8.

Ultra

Thanks for the comment. But The link talks about L2 interface. My question is related to the port between the processor (actually processor's load/store queue) and its L1 data cache. There is no bus between the processor and L1 cache, since these two are connected directly. – Collins

I always thought they share the same properties. – Ultra