PoU and PoC in cache maintenance operations in arm

Question

When reading ARM arch. ref. manual v7, I've found two concepts; point of coherency (PoC) and point of unification (PoU).

For PoC, it looks like the point that all agents (i.e., CPU cores) can see the same copy of memory.

For PoU, it looks like the point that all agents (in this case, CPU cores and MMU) can see the same copy of memory.

I have several follow up questions:

1. Is my understanding correct?

2. If so, If I issue DCCMVAC (Data cache clean MVA to PoC) with giving MVA to 0x40000000, (and let say PoC happen to be 0x70000000),

   all cache entries between VA of 0x40000000 and 0x70000000 are cleaned?

3. Then, if I issue DCCMVAC with MVA 0x0, all data cache entries are cleaned?

4. PoU sounds like that MMU itself has its own data caches (not TLB) for page table walk inside main memory. Is this correct?

Quinby

Instead of MMU think/learn about TLB (that's your 4th item). If system is advanced PoC can be L1 where SCU keeps shareable memory coherent. PoU can be L2 - as you said where everyone has the same copy. – Twelfth

Oh, what I meant (in 4th item) is when MMU accesses the page table in main memory (when TLB miss happens), does it directly access to main memory or it accesses some kind of data cache? – Quinby

TLB is MMU's cache (afaik) and TLB doesn't have a cache. – Twelfth

TLB is MMU's cache for storing va<->pa mappings. If there is missing entry in TLB, MMU has to walk the page table inside the main memory. What I'm curious about is this moment (MMU accesses the main memory). I've edited the question for avoiding confusion. – Quinby

There is no such cache as MMU's data cache. You can read cortex-a series programmers guide for some extra information. – Twelfth

Answer 1

According to ARM training materials:

The PoU (Point of Unification) for a processor is the point (physical location within the hardware) where the instruction and data caches and the translation table walks of the processor are guaranteed to see the same copy of a memory location. For example, a unified level 2 cache would be the point of unification in a system with Harvard level 1 caches and a TLB (to cache page table entries). If no external cache is present, main memory would be the Point of unification.

The PoC (Point of [system] Coherency) is the point at which all blocks (for example, CPUs, DSPs, or DMA engines) which can access memory, are guaranteed for a particular address to see the same copy of a memory location. Typically, this will be the main external system memory.

Diaz

Answer 2

it's one old case, however, adding some comments in case of someone's search.

in my opinion, PoU and PoC are coined by ARM to define one level for cache maintenance. the definition of PoC and PoU is in ARM ARM specification, while its ARMv8 programming guide (not ARM spec) gives some diagram for better understanding: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/ch11s04.html

one point is ,under ARM V8 processor's implementation, Iside can snoop Dside, for example, if there is one Icache miss, it will check Dcache, so you could treat PoU as the level of L1 cache. while other ARMv8 processor may not have this behaviour.

back to the original questions: 2) DCCMVAC 0x40000000, it will do cache clean to PoC about this address, mostly one cache line PoC is defined by SoC implementation, not by address.

3) considering Q2, DCCMVAC 0x0, only applies to one cache line. if you want to clean and invalidate the whole cache, you need use by set/way to walkthrough the whole cache.

4) PoU has nothing to do with MMU. MMU hardware block owns some buffers to save TLB entries, it's one common practice, as for pagetable, which is built by software as in the memory, normally it's defined as normal memory type, so it could be in the cache during setup by CPU instruction, or walk by MMU hardware walk unit.

Splashdown