The documentation for imul states that:
SF is updated according to the most significant bit of the operand-size-truncated result in the destination.
For a 64-bit operation, then, my understanding is that SF = (a * b) >> 63
, or more simply if a
and b
are signed, SF = a * b < 0
.
However, I'm getting an unexpected result multiplying two large numbers:
mov rax, 0x9090909090909095
mov rdx, 0x4040404040404043
imul rax, rdx
The result of 0x9090909090909095 * 0x4040404040404043
is 0xefcba7835f3b16ff
. It has the sign bit set, however the SF flag is cleared after the imul
instruction. What's going on?
This was cross-posted to the Intel forums some time ago.
SF ← TMP_XP[32];
, should be31
obviously. What does Intel have to say about this instruction, by the way? – Refreshment