Printing packed structs in System Verilog

Question

I have a packed struct defined as shown below

typedef struct packed {
    logic bit1;
    logic [7:0] byte1;
} MyPackedStruct;

MyPackedStruct myPackedStruct;

Is there any SV built in function that I could use to print the structures similar to above but having many more fields, without having to write my own method to print each of the fields using a

$display(...,myPackedStruct.field_name)?

Gentianaceous

Answer 1

You can use %p - pretty print:

$displayb("%p",myPackedStruct);

'{bit1:x, byte1:xxxxxxxx}

which will print it as an assignment pattern, but you will not be able choose the fields or their ordering, or apply any other individual formating. %p is good for quick and easy displays, but most people eventually wind up writing a method to format it exactly the way they want it.

Intoxication

This is also valid for printing dynamic arrays. – Hallel

You can use it for any unpacked array, but any large array you will probably want to format in some kind of loop. – Intoxication

Cannot edit this post: "Suggested edit queue is full" But $displayb should be $display – Meganmeganthropus

@Meganmeganthropus $displayb is what I wanted to get everything printed in binary radix. – Intoxication

OK! Sorry for the definitive comment I put, then. Do you know where I can find the doc about displayb in the LRM ? – Meganmeganthropus

Section 21.2 Display system tasks in the 1800-2017 SystemVerilog LRM – Intoxication

Answer 2

You can use the %p formatting element.

$display("%p", myPackedStruct);

Output from Modelsim:

 # '{bit1:x, byte1:x}

See section 21.2.1.7 Assignment pattern format in the IEEE 1800-2012 SystemVerilog language spec.

Adessive

+1 Thanks for the section reference to the spec. I missed this section somehow. – Gentianaceous