Avoiding CortexM Interrupt Nesting

Question

I want to avoid nested interrupts at the interrupts entry in a CortexM based microcontroller.

To achieve this I have an assembly file containing interrupt vectors and first instruction of each vector is the instruction (CPSID I) to disable interrupts globally. After every individual interrupt handler(written in C), execution returns to a common assembly routine which re-enables the interrupts with instruction CPSIE I and return from Interrupt/Exception process is triggered with instruction BX LR.

On interrupt entry CortexM auto-stacks the exception frame, containing volatile context (Caller saved context) and jumps to the first instruction of the exception/interrupt vector.

According to ARM Info Center it takes at least 12 cycles to complete the stacking process and fetching of the address of the first instruction of target vector from NVIC (Nested Vectored Interrupt Controller). If another higher priority interrupt arrives during the stacking process(It is a Late arrival case), stacking process is continued but the higher priority process will be serviced first.

My first question is, is this Late Arrival case considered as nested interrupt scenario i.e the LR register will be 0xFFFF FFF1 (Considering Basic Frame only)?

Second, Is it possible that an exception can be accepted between the stacking process is completed and beofre CPSID I gets executed?

Gambia

Answer 1

The simple way to avoid nesting would be to have all interrupts at the same priority.

You could still prioritise them using sub-priorities if you like but I am not sure this would give you any benefit.

Late arrival is a bit like nesting, except the higher priority interrupt will run before the lower priority interrupt. The lower priority interrupt will tail chain onto the higher priority interrupt.

Yes it is possible for a higher priority interrupt to be accepted before you execute CPSID I. Depending on the timing you would either get a late arrival or nesting scenario.

Maximalist

yes I know about the tail chaining of low priority interrupt after handling the high priority interrupt but just to clarify I would like to ask: In case of Late-Arrival, will the pattern in LR be 0xFFFFFFF9 while inside the handler of late arriving high priority or 0xFFFFFFF1 ? – Gambia

It's immaterial: your proposed solution still contains a race, where a full switch to an ISR could be interrupted by another IRQ before the CPSID instruction has been executed, so this answer is the only correct one. – Columbic