packed vs unpacked vectors in system verilog

Question

Looking at some code I'm maintaining in System Verilog I see some signals that are defined like this:

node [range_hi:range_lo]x;

and others that are defined like this:

node y[range_hi:range_lo];

I understand that x is defined as packed, while y is defined as unpacked. However, I have no idea what that means.

What is the difference between packed and unpacked vectors in System Verilog?

Edit: Responding to @Empi's answer, why should a hardware designer who's writing in SV care about the internal representation of the array? Are there any times when I shouldn't or can't use packed signals?

Imaimage

Answer 1

This article gives more details about this issue: http://electrosofts.com/systemverilog/arrays.html, especially section 5.2.

A packed array is a mechanism for subdividing a vector into subfields which can be conveniently accessed as array elements. Consequently, a packed array is guaranteed to be represented as a contiguous set of bits. An unpacked array may or may not be so represented. A packed array differs from an unpacked array in that, when a packed array appears as a primary, it is treated as a single vector.

Kobold

>A packed array differs from an unpacked array in that, when a packed array appears as a primary, it is treated as a single vector. Whats the meaning of this sentence? – Timothy

Answer 2

Before knowing what exactly packed and unpacked arrays are, lets also see how you can know which array is what, just by their declaration. Packed arrays have an object name which comes after the size declaration. For example:

bit [3][7] a;

where a is a 28-bit vector subdivided into 3 7-bit subfields.

Unpacked arrays have an object name which comes before the size declaration. For example:

bit b [3];

where b is a 3-bit wide vector.

Packed arrays make memory whereas Unpacked don't. You can access/declare unpacked arrays like this also

reg unpacked_array [7:0] = '{0,0,0,0,0,0,0,1};

You can mix both packed and unpacked array to make a multidimensional array. For example:

bit [3:0][7:0] a [2:0].

It makes an array of 4 (i.e. 4*8) bytes with depth of 3.

Photocopier

"Packed array make memory whereas Unpacked dont." What does that mean? There are plenty of FPGA synthesis tools that will convert unpacked arrays into some kind of memory (either FFs or RAMs). – Plenary

Answer 3

Packed array are mainly used for effective memory usage when we are writing a [3:0][7:0]A[4:0] which means in 32 bit memory locations 4slices each of 8 bit are packed to form a 32 bit. The right side value means there are 5 such slices are there.

Team

Answer 4

bit[3:0] a -> packed array The packed array can be used as a full array (a='d1) or just part of an array (a[0]='b1)

bit a [3:0] -> unpacked array The unpacked array cannot be used as a[0]='b1, it has to be used as full a={8{'b1}}

Bourse

Answer 5

A good explanation is given at verification academy.

A packed array of n vectors can be imagined as an array of single row and n columns.

Whereas an unpacked array of "n" vectors and "m" unpacked dimensions can be imagined as a matrix/2D array of n columns and m rows.

Vav

Answer 6

Unpacked arrays will give you more compile time error checking than packed arrays.

I see unpacked arrays on the port definitions of modules for this reason. The compiler will error if the dimensions of the signal are not exactly the same as the port with unpacked arrays. With packed arrays it will normally just go ahead and wire things the best it can, not issuing an error.

Paring

Answer 7

bit a [3:0] -> unpacked array The unpacked array cannot be used as a[0]='b1, it has to be used as full a={8{'b1}}

---> in above statement a[0] ='b1; will work for unpacked array , it won't work where some portion of the unpkd arry[eg logic unpkd [8];] like unpkd = 5'h7; assignment same will work for pkd array --> unpkd = unpkd +2; won't wok for unpkd will work for pkd

Radom