I am getting the following error running make:
Makefile:168: *** missing separator. Stop.
What is causing this?
Make error: missing separator
As indicated in the online manual, the most common cause for that error is that lines are indented with spaces when make expects tab characters.
Correct
target:
\tcmd
where \t is TAB (U+0009)
Wrong
target:
....cmd
where each . represents a SPACE (U+0020).
You can use .RECIPEPREFIX to change the character make uses. See: gnu.org/software/make/manual/html_node/… –
Johppa
To confirm, I just ran into this myself. Most editors/IDEs can help spot this. For example, in IDEA, go to the View menu, choose "Active Editor", "Show Whitespaces". I can't believe that spaces vs. tabs is still a thing in (checks notes) 2022. –
Quartus
I had a string variable that contained newlines - not by choice. Snuck in via
execute_process, fixed with OUTPUT_STRIP_TRAILING_WHITESPACE seeing as the output is single-line. Infuriatingly bad error message though –
Hyetography Just for grins, and in case somebody else runs into a similar error:
I got the infamous "missing separator" error because I had invoked a rule defining a function as
($eval $(call function,args))
rather than
$(eval $(call function,args))
i.e. ($ rather than $(.
What? :) I guess you didn't have
0x20 "space" there, is that correct? –
Inherited @Inherited The placement of
$ –
Unwritten This is a syntax error in your Makefile. It's quite hard to be more specific than that, without seeing the file itself, or relevant portion(s) thereof.
For me, the problem was that I had some end-of-line # ... comments embedded within a define ... endef multi-line variable definition. Removing the comments made the problem go away.
Thank you. I didn't know comments in
define directive are treated literally. Actually the behavior is not explain in the documentation. (For clarity: Embedding a number sign # within the directive isn't itself a syntax error. But it is just not interpreted as a start of a comment, so doing that is admittedly error-prone.) –
Caylacaylor In my case, this error was caused by the lack of a mere space. I had this if block in my makefile:
if($(METHOD),opt)
CFLAGS=
endif
which should have been:
if ($(METHOD),opt)
CFLAGS=
endif
with a space after if.
just why, why... –
Kassab
In my case, I was actually missing a tab in between ifeq and the command on the next line. No spaces were there to begin with.
ifeq ($(wildcard $DIR_FILE), )
cd $FOLDER; cp -f $DIR_FILE.tpl $DIR_FILE.xs;
endif
Should have been:
ifeq ($(wildcard $DIR_FILE), )
<tab>cd $FOLDER; cp -f $DIR_FILE.tpl $DIR_FILE.xs;
endif
Note the <tab> is an actual tab character
My error was on a variable declaration line with a multi-line extension. I have a trailing space after the "\" which made that an invalid line continuation.
MY_VAR = \
val1 \ <-- 0x20 there caused the error.
val2
In my case error caused next. I've tried to execute commands globally i.e outside of any target.
UPD. To run command globally one must be properly formed. For example command
ln -sf ../../user/curl/$SRC_NAME ./$SRC_NAME
would become:
$(shell ln -sf ../../user/curl/$(SRC_NAME) ./$(SRC_NAME))
In my case, the same error was caused because colon: was missing at end as in staging.deploy:. So note that it can be easy syntax mistake.
I had the missing separator file in Makefiles generated by qmake. I was porting Qt code to a different platform. I didn't have QMAKESPEC nor MAKE set. Here's the link I found the answer:
https://forum.qt.io/topic/3783/missing-separator-error-in-makefile/5
Just to add yet another reason this can show up:
$(eval VALUE)
is not valid and will produce a "missing separator" error.
$(eval IDENTIFIER=VALUE)
is acceptable. This sort of error showed up for me when I had an macro defined with define and tried to do
define SOME_MACRO
... some expression ...
endef
VAR=$(eval $(call SOME_MACRO,arg))
where the macro did not evaluate to an assignment.
I had this because I had no colon after PHONY
Not this,
.PHONY install
install:
install -m0755 bin/ytdl-clean /usr/local/bin
But this (notice the colon)
.PHONY: install
...
Following Makefile code worked:
obj-m = hello.o
all:
$(MAKE) -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
$(MAKE) -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
Please elaborate –
Protanopia
So apparently, all I needed was the "build-essential" package, then to run autoconf first, which made the Makefile.pre.in, then the ./configure then the make which works perfectly...
completely not understandable answer, not applicable to the question in any way –
Maculation
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missing separatoris just make's version of a generic syntax error, or "I have no idea what the heck you are trying to do here". It's not really feasible to provide a better error because make can't figure out what this line is supposed to be. Make's parser works with "separators": if it finds a=then it's a variable assignment, if it finds a:then it's a rule, if it starts with a TAB (or.RECIPEPREFIXcharacter) it's a recipe. If none of those things then... it has no idea. – Mesognathous