Please note that this is not a duplicate of the other questions named generic makefile.
I have followed all of the instructions on other questions about generic makefiles, and this is the code I have come up with from that:
CFLAGS = -c
CC = cc
SOURCES = $(wildcard *.cc)
OBJECTS = $(patsubst %.cc,%.o,%(SOURCES))
EXEC = run
all: build clean
build: $(OBJECTS)
$(CC) $(OBJECTS) -o $(EXEC)
%.o: %.cc
$(CC) $(CFLAGS) $<
clean:
rm *.o
However, when I execute make
with a file called test.cc
in my directory, it gives me the followig error:
cc -o run
cc: error: no input files
*** Error code 1
Stop.
make: stopped in /somewhere
Please note that I am on FreeBSD and the make
and cc
commands are the ones which come with the OS.
CC = cc
is very likely a C compiler. – Disconsider