TAS instruction 68000

Question

To handle concurrency in an M68000 assembly program, I need to understand how the TAS instruction works.

I don't really care about the theoretical description that I can see from the manual (e.g. http://68k.hax.com/TAS). More than anything I would like to see some examples.

Adebayo

easy68k.com/paulrsm/doc/dpbm68k3.htm describes what it's for and how you'd use it, in the "Instructions for Shared Resources" section. syllabus.cs.manchester.ac.uk/ugt/2015/COMP35112/Lect7.pdf has a lock-taking spin-loop example. – Charlsiecharlton

Answer 1

Actually, there isn't much to this instruction. A typical piece of spin lock code in 68k assembly could look like that:

        lea.l  spinLock(pc),a0
getLock:
        tas   (a0)
        bne.s getLock
        bra   haveLock
spinLock 
        dc.b  0

The code sets the MSB of the byte at spinLock, and loops around until the zero flag is set (telling you the bit was not set before, i.e. no other piece of code has already acqiured the lock). The important thing is the TAS instruction is atomic, that is, it cannot be interrupted by other code (like an ISR, for example) between the bit test and the set.

Dett

Every instruction is atomic wrt. interrupts and thus ISRs. More interesting is that it's atomic even wrt. DMA accesses and things other cores (if any) are doing. But yes, getting the test and the set done in one instruction, setting flags according to the old value, is something you can't do with another single instruction. – Charlsiecharlton

@PeterCordes Of course every instruction is atomic - as opposed to having the test and the set instruction in two instructions - which is obviously not atomic. BTW I'm not aware there ever was a multicore 68k. – Dett

It's not quite "of course": the memory location could be written by DMA between the read and the write, if it wasn't atomic. But yes fair point that there were no multi-socket SMP m68k systems so the other access can't be coming from another core. Amusingly, while googling for this, I found the old Linux 2.0 / 2.1 SMP FAQ saying "MIPS, m68k and ARM does not support SMP; the latter two probly won't ever." Turns out ARM had other plans. :P – Charlsiecharlton

Hmm, apollo-core.com/knowledge.php?b=4&note=6171&z=UfZpZv suggests a multi-core m68k might be possible in an FPGA soft-core. – Charlsiecharlton

@PeterCordes On a 68k system, it's "of course" (except the Amiga, where the non-atomicy is caused by a custom chip bug) – Dett

While there may or may not have been multicore 68k, there have been systems with more than one 68k working on the same bus. In such a system, using a bset instead of tas can show the non-atomic nature of bset: both processors can read the old value and write the new value for the spinlock example, and both processors would proceed thinking they own the lock. Tas uses a locked read-modify-write cycle that prevents other processors from reading/writing to the value in question until the instruction has completed. – Rest

@Dett I believe it's also bugged on Sega Genesis as well, as I can't seem to get it to work correctly. Unfortunately I can't remember the details and searching "genesis tas bug" on google just gives me a bunch of tool-assisted speedruns so unfortunately I can't really confirm this at the moment – Lowpressure