If we have two cores which read and write to different memory position in the same cache block, both cores are forced to reload that cache block again and again, although it is logically not necessary. This is what we call false sharing.
However, what if the cores never read from that cache block, but only write? Imagine the two cores just set some bits in the same cache block, but they don't have to read from the block, because the bit information they set is only needed in a later phase of the program.
Does false sharing only occur if the cores read and write on the same block, or does it also occur if both only write to it?
perf c2c
I came to a different conclusion. See here: #78963265 – Whore