Is the Z80 NMI reentrant?

Question

From what I could gather the Z80 NMI interrupt (0x66) is triggered from an edge detection of the NMI pin. What happens when another edge is detected when still inside the NMI handler code (RETN has not executed yet)?

Is NMI reentrant and will the Z80 just push the current address on the stack and start at 0x66 again?

Mew

Thank you for the link. Very useful. – Mew

Answer 1

My reading is that a second NMI would interrupt processing of the first. The only special thing that NMI processing does to avoid additional interruption is back up IFF1 to IFF2 and then set IFF1 (with RETNs special feature being restoration in the other direction). But that won't prohibit NMIs. So there is no mechanism by which a future NMI will be ignored.

This is lightly backed up in the literature, albeit subtlely — e.g. "This negative edge triggered interrupt cannot be disabled under program control and will be accepted at any time by the CPU to be honored at the completion of the current instruction (if Bus Request not pending)"; emphasis added but also note that bus request has been pulled out as a special case with no mention of an existing NMI.

Encampment

And not so subtly backed up by the name. NMI - Non-Maskable Interrupt. In other words, you can't stop it from happening by disabling (masking) interrupts with DI. – Skunk

The wording back up IFF1 to IFF2 is likely wrong. If IFF1 was really copied into IFF2 on NMI, then the nested NMI interrupt would destroy the previous value of IFF2. But tests suggest this does not happen: raine.1emulation.com/archive/dev/z80-documented.pdf – Liard