Sequence of micro-operations for operations?

Question

Consider the following sequence of micro-operations.

  MBR ← PC
  MAR ← X  
  PC ← Y  
  Memory ← MBR

Which one of the following is a possible operation performed by this sequence?

1. Instruction fetch
2. Operand fetch
3. Conditional branch
4. Initiation of interrupt service

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Answer is option (4).

My attempt :

1. Instruction fetch : Fetch instruction: Read instruction code from address in PC and place in IR. ( IR ← Memory[PC] )
2. Operand fetch : Fetch operands from memory if necessary: If any operands are memory addresses, initiate memory read cycles to read them into CPU registers. If an operand is in memory, not a register, then the memory address of the operand is known as the effective address, or EA for short. The fetching of an operand can therefore be denoted as Register ← Memory[EA]. On today's computers, CPUs are much faster than memory, so operand fetching usually takes multiple CPU clock cycles to complete.
3. A conditional branch instruction causes the location counter in the PSW to be set to the address specified in the register or the register plus a 12-bit offset, if a condition is satisfied (and the register is not 0)
4. An interrupt service routine (ISR) is a software routine that hardware invokes in response to an interrupt. ISRs examine an interrupt and determine how to handle it. ISRs handle the interrupt, and then return a logical interrupt value.

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Can you explain in sequence of micro-operations for operations given in option?

Inexpugnable

what is the question? – Merrick

I'm asking for micro-operations such given MBR ← PC MAR ← X PC ← Y Memory ← MBR for Initiation of interrupt service . Similarly , if you can give such correct codes for other options (1),(2) and (3) ? – Inexpugnable

I am slightly puzzled, isn't memory <- MBR a memory write? None of the operations listed do a memory write. – Schematize

It could be interrupt, if the return address is written in some predefined place in memory, but I doubt... – Stenger

@Stenger that actually makes sense, since MBR has been assigned the PC earlier. – Schematize

Can you explain in sequence of micro-operations for operation given in options? – Inexpugnable

There's a perfectly good answer to this same question here: gateoverflow.in/1539 – Acerbate

@eh9, I'm there, that site contains previous year competitive exam GATE's papers. Those who written answers there all are students, I also written some answers there. I seen SO and its all community is better than that in respect to reliable answer. – Inexpugnable

Answer 1

This question uses notation from one of William Stalling's Computer Organization and Architecture textbooks. The question itself does not contain enough background material for someone unfamiliar with Stalling's textbook to answer it (I do not own Stalling's textbook, or know which version this question references).

However, after seeing the comment that pointed to an answer at another site, I Googled for "rules for clock cycle grouping". That led to a bunch of links that pointed to various different sets of slides.

The third link for me was to a powerpoint presentation which included a slide that I have copied below as an image. There was a slide that explained what MAR and MBR stand for:

Memory Address Register (MAR)

• Connected to address bus

• Specifies address for read or write op

Memory Buffer Register (MBR)

• Connected to data bus

• Holds data to write or last data read

So it appears that what is happening is that first the PC is placed in MBR. Next the address for where the PC will be saved is copied from X to MAR. In the same cycle the PC is set to the start of the interrupt service routine which is available in Y. Finally the data in MBR is transferred on the bus to memory.

Lied

Thanks for explanation. – Inexpugnable

I couldn't understand how can two different addresses pass at the same time in one clock cycle(clock cycle t2) to registers MAR and PC through one address bus. – Coercion