Minimum Page Frames

Question

What determines the minimum number of page frames that must be allocated to a running process in a virtual memory environment.

I found the the answer to the above question is instruction set architecture but couldn't understand reason behind it.

please explain.

EDIT : The question is on the following link http://www.geeksforgeeks.org/archives/4036 (see question 3), i'm not able to understand the logic behind the answer.

Malda

This totally depends on what operating system you are talking about... there is no real answer to that question. The minimum I would say is enough size to store the memory footprint of the binary and some room for a stack. If the program uses the heap it would need some more. A page is typically 4096 bytes so just divide all that should be included and divide it by 4096 and you would get an approximation. Don't know what instruction set architecture has to do with that... – Cloistered

on the following link geeksforgeeks.org/archives/4036 see the third question. i'm not able to understand the logic behind the answer. – Malda

There is something seriously wrong with that question. He does not seem to talk about page frames at all. What I think it could be about is the number of bytes needed for each entry in the TLB or something like that... My suggestion is to forget about it. – Cloistered

Answer 1

yes ISA does play a role.
Imagine this hypothetical condition if the ISA supports an instruction(like mov in x86) which can take an operand after 3 levels of indirection( recall x86's indirect addressing mode). Lets call this system A.
On another system you can have max of 2 levels of indirection call it B.

On A and B if we give 4 as the minimum number of frames see what happens. B runs fine not A here's the reason:
when an instruction which has 3 level of indirection in its operand is loaded into the cpu for execution, remember we only have 4 frames for this process,assume this scenario
frame 1 will be for the instruction itself.
frame 2 will be for the 1st level of indirection the operand is in another page
frame 3 will be for the 2nd level of indirection maybe this was not in the address range of previously allocated frame.
frame 4 the same happens with the next level of indirection.
Now recall pipeline , only after the operand fetch is done we can go to the next execution stage, but we don't have the final operand we only have the address of where it in the frame 4 , now you get a page fault, so you remove one of the previously allocated frame to process and restart the instruction which caused the fault , but again the same thing happens. The system B doesn't have this problem.

As far as i recall this is the way ISA plays a role in deciding minimum number of frames for a process. Refer galvin i think the book covers this in virtual memory section.
But this is in theory , I don't know how the process is in a real system like linux.

Cheers :)

Edit:- As given in the link you pointed the instruction may cross page boundary

Manicure