NMI and IRQ interruptions

Question

I am trying to find information about how the 6502 proccesor handles interruptions, but I am very confuse. I have seen some examples about it, but It is like a normal subrutine.

I have some experiences with the 8086 processor, and I remember that there are some codes to handle different interruptions.

Firstly, I will be very thankful if someone could explain me differences between NMI and IRQ with some code. And even more, If you get me more information about handling interruption for (for example) handling a keyboard interruption.

Melosa

An NMI (non maskable interrupt) is an interrupt that cannot or should not be disabled as they are triggered for very serious problems. IRQ's are normal interrupts that can be enabled/disabled and can be used for different purposes (for example timer interrupt). I'm not too familiar with 6502 but if you want code examples I can give them for x86. – Spherics

Answer 1

There are two separate interrupts: maskable and non-maskable. The 6502 will sample these one cycle before the end of each instruction.

If the NMI line has become active (it's edge triggered) then it will perform the NMI routine after this operation completes.

Otherwise, if the IRQ line is active (it's level triggered) and the interrupt disable flag isn't set then it will perform the IRQ routine after this operation completes.

In both cases it'll read the jump vector, push the current program counter and status register to the stack, set the interrupt disable bit and jump to wherever the vector indicated. From memory, that all takes seven cycles.

As well as pushing the status register there's a difference in who is considered responsible for incrementing the the program counter so you use RTI to return from an interrupt handler rather than RTS.

The NMI vector is read from FFFA/FFFBh, IRQ from FFFE/FFFFh. The reset vector is between and you could, at a distance, view reset as a kind of NMI that you can't return from.

BRK is supposed to sort of simulate an IRQ but doesn't do it very well.

So the intended arrangement is: NMIs for anything that should always be serviced now. IRQs for anything that's fine to wait a while. Quite a lot of micros don't wire up NMI at all because then you've always got to have a working handler, but that's far from universal.

Staciastacie

could you show me a basic example of irq and nmi in 6502 assembler? – Melosa

Easiest example is one that looks like: nmi: rti which effectively does nothing. Not very useful, you'll want to look at NES development which uses the NMI for updating the screen. – Pincas

Answer 2

The NMI (non-maskable interrupt) and IRQ (interrupt request) are separate physical pins on the CPU package.

When an interrupt is triggered, execution jumps to a memory location pointed to by 0xFFFE and 0xFFFF (for IRQ). For most processors, the registers should be pushed to the stack using:

PHA
PHX
PHY

SEI can be used to disable IRQs, but not NMIs. CLI will enable them again.

6502.org has a lot of tutorials.

Eyecatching

Isn't that reversed? "If protected-mode virtual interrupts are not enabled, CLI clears the IF flag in the EFLAGS register. No other flags are affected. Clearing the IF flag causes the processor to ignore maskable external interrupts." – Gretna

@Cees, that’s an x86 reference. Completely unrelated to the question. – Straitlaced

Answer 3

In answer to your question, both NMI and IRQ operate in an almost identical way on the 6502. It runs is a seven cycle operation that can be found in the MOS 6502 Programming Manual, Chapter 9, which covers all of the Interrupt type instructions. As noted by others, NMI stands for Non-Maskable Interrupt and IRQ stand for Interrupt Request (as it can be masked). NMIs use vector address FFFA-FFFB while IRQs and BRKs both use FFFE-FFFF.

Bear in mind that while the JSR instruction stores the PC register as it is pointing to the last byte of the JSR instruction, the NMI and IRQ operations store the first byte of the next instruction to be executed when the interrupt ends. This is part of why RTS and RTI cannot be used interchangeably.

BRK works similar to IRQ, but with two exceptions. First, though BRK is only a one byte instruction, the PC register is advanced twice before it is stored, so the return address will be the second byte after BRK. Second, bit 4 of the value for the P register (the status register) that is stored on the stack is set, while it is cleared for IRQs. Note that this bit is not actually wired internally, so if you use PHP, then PLA to read the status register, bit 4 will always be set, since data lines on the 6502 default high.

The MOS 6502 Programming Manual is great for understanding how the 6502 operates, since it outlines how every type of 6502 instruction and interrupt is executed.

Principe

As a little more clarification for how the 6502 handles interrupts, the NMI and IRQ lines are active low, which is also why the I flag in the P register must be clear for IRQs to generate. The internal logic uses a NOR gate to determine whether or not an IRQ will be acknowledged. – Principe