I have the following code for checkboxes,
### Pre-requisites
- [ ] You should have done the Verilog parsign of all the files (../parse_verilog/)
- [ ] You should have generated CDFGs for all the modules (../gen_cdfg/)
which appears in Bitbucket like the following (with bullets instead of checkboxes)
What could be the reason?
Update (2-Jul-2020) If Bitbucket enables this feature, please post a comment below.