In my embedded project am using JTAG interface to download the code and to debug the downloaded application. But I don't know what is happening inside the JTAG set up.
Can anyone please give me basic idea/flow(high level view) of the JTAG set up which will really help me to understand my development system better.
To add to Cliffords answer, there are some pictures here:
http://www.fpga4fun.com/JTAG2.html
The tap controller state machine is something you will see published ad nauseum. It is really the key to JTAG. As Clifford said you access on chip debug registers. The tap controller state machine is generic to all JTAG supported devices, but the address, length, etc of the registers you can get to through JTAG. And the sequence of things you have to read or write in order to do something useful varies widely from vendor to vendor. Some ARM Technical Reference Manuals (for various cores) for example have a Debug TAP controller chapter, with this picture and with the gory details on the procedure for reading and writing a register or memory or halting the processor, etc.
When applied to processor debug (since JTAG is more generally used as a boundary scan test interface), JTAG is simply a means of communicating with the device's on-chip debug block and memory interface.
JTAG itself is a simple synchronous serial data bus. JTAG devices on the "JTAG chain" simply clock the data through a shift register until the required data is in the register. The number of clocks required to get the data into the on-chip debug register(s) depends on the length of the shift register(s) and the length of the registers of any preceding devices on the same debug chain. JTAG operates in a loop so that the data-out matches the data-in with a delay equal to the total bit length of the chain.
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