Purpose of address-spaced identifiers(ASIDs)

Question

I am currently studying Operating Systems by A Silberschatz, P Galvin, G Gagne.

I am studying memory management strategies, and on section where they introduce Translation Look-aside Buffer (TLB).

Some TLBs store address-space identifiers (ASIDs) in each TLB entry. An ASID uniquely identifies each process and is used to provide address-space protection for that process. When the TLB attempts to resolve virtual page numbers, it ensures that the ASID for the currently running process matches the ASID associated with the virtual page. If the ASIDs do not match, the attempt is treated as a TLB miss.

Above is a quote from the textbook explaining ASID.

I am a bit confused as TLB miss means the logical address weren't able to be matched in TLB, so it has to be checked with Page table to head towards the physical memory.

That being said, ASID is an extra bits for each entry in TLB to check if the process that is accessing that entry belongs to the process.

What I am wondering is, when ASID is used to refuse the process, shouldn't it trap, instead of TLB miss? TLB miss will forward the process to page table, where the logical address for the process will be able to be mapped to certain address in main memory.

Please help me where I am understanding incorrectly.

Thanks!

Psychomotor

It is not completely clear what are you asking about. ASID is an additional field in virtual address in TLB, which are determine the PID of the process this address belongs to. TLB miss is a situation, where you have no such ASID+VA combination in TLB cache, so thus you need to refer a page tables. – Gena

@AlexHoppus Thanks for the comment. I have updated the question, which might be better explained.. Let me know if you are still unclear. – Psychomotor

"What I am wondering is, when ASID is used to refuse the process, shouldn't it trap, instead of TLB miss?" no it shouldn't. Why it is wondering you? – Gena

@AlexHoppus My understanding of TLB miss is that it will simply take more time to map logical address into physical address. While process tries to retrieve instruction or data from physical address, and process having no right to access this address (as ASID was used to refuse the requesting process), the result should be a trap or error, not simply TLB miss. TLB miss is.. I am repeating myself. – Psychomotor

Answer 1

Let's say you have two processes running on a system. Process A has its 2nd page mapped to the 100th page frame and Process B has its 2nd page mapped to the 200th page frame.

So now the MMU needs to find page #2, but does not want to read the page tables again. Does it go to page frame 100 or page frame 200?

There are at least two ways of handling that problem. One is to flush the cache whenever there is a process switch.

The other is to assign some unique identifier for each process and include that in the TLB cache entries.

I am a bit confused as TLB miss means the logical address weren't able to be matched in TLB, so it has to be checked with Page table to head towards the physical memory.

To translate logical page #X to a physical page frame:

1. Look in the TLB for #X. If it's not there, go to the page table.
2. [#X exists] Is there an entry for #X with an ASID that matches the current process? If not, go to the page table.
3. Use the page mapping in the TLB.

What I am wondering is, when ASID is used to refuse the process, shouldn't it trap, instead of TLB miss?

Then you'd get traps the first time the process accessed a page and the program would crash.

Overcasting

Answer 2

Though one year has passed, I happen to have the same problem as yours. And I found a detailed explanation of TLB miss:

For software-managed TLB, when the machine encounters a TLB miss, the hardware would raise an exception (trap) to the OS (switched to kernel mode), and the trap handler for TLB miss would then look up the page table and update the TLB.

After that, the handler would return to the interrupted instruction (try the instruction that caused the exception again), which would yield TLB hit this time.

operating system three easy pieces, the explanation is at section 19.3

Halidom

+1 for adding that it updates the TLB with correct page number and memory frame which will age out some other processes entry. – Senaidasenalda

Answer 3

I would think that a TLB miss should trap to the OS (or virtual memory manager) when that TLB was the final TLB for physical/real memory but there are also TLBs for L1 cache, L2 cache, and L3 cache. When a cache TLB has a miss, there may be a hardware page table walker that can resolve the TLB miss much faster than a context switch to the OS (which would also pollute the caches and TLBs).

Multiple processes share a L3 TLB on a multicore processor and two processes share a L1 TLB and L2 TLB when hyperthreading is available and enabled. Each process has its own independent virtual address space, which the TLBs must distinguish.

Mortician