How many AMD exclusive instructions are there on zen 3 CPUs?

Question

How many instructions on zen 3 CPUs are exclusive to AMD?

I am aware of only 3: mwaitx, monitorx, and clzero

Also, the 3DNow! and lwp instruction sets were once AMD exclusive but they have since been removed.

Witchhunt

I'm sure there are loads. Not something you'll find in instruction manuals. – Bomar

Answer 1

Indeed, the three instructions MWAITX, MONITORX, and CLZERO are supported on AMD Zen3 and no Intel processor (yet).

Zen3 also supports the SSE4a instruction set composed of 4 instructions (EXTRQ, INSERTQ, MOVNTSD and MOVNTSS) which is not supported by Intel.

It also supports the AMD-exclusive SEV-SNP instruction set (Secure Encrypted Virtualization - Secure Nested Paging) composed of 4 instructions (PSMASH, PVALIDATE, RMPADJUST and RMPUPDATE). It should also support older related instruction sets like SEV-ES (Secure Encrypted Virtualization - Encrypted State) composed of the instruction VMGEXIT. All of this is part of AMD-V (all these abbreviations are a bit confusing). That being said, such instruction are typically available only on EPYC processors and not Ryzen ones. Moreover, AFAIK, Intel has similar instruction sets for this like for example Total Memory Encryption. The alternative of AMD-V is Intel VT-x.

Furthermore, the skinit instruction set (for security), which is (also) a part of AMD-V and composed of the 2 instructions SKINIT and STGI, is also AMD-specific. It appears to be available on some Zen processors (including Zen3) but it is not clear exactly which one (it at least targets AMD Ryzen PRO processors).

Like 3DNow!, the FMA4 instruction set was exclusive to AMD. It was certainly supported on Zen1 though it was not officially the case (not present in any AMD Zen-related document nor provided by the CPUID instruction). Indeed, multiple users reported the instruction set was working correctly (see [1], [2] and [3]). Zen2 and Zen3 certainly do not support it at all (see the comment of @PeterCordes). Officially, the AMD's TBM, FMA4, XOP and LWP instruction sets (previously available on the Bulldozer architecture) are not supported on all Zen architectures (see this).

For more information, you can check the AMD's manual (vol 3, rev 3.33).

Enchantress

Last I heard (from Mysticial), FMA4 worked fine on Zen1 even though not reported by CPUID. (There were rumours that it didn't always work perfectly, but those all stemmed from one unsubstantiated report which was presumably user error.) And FMA4 faulted as an illegal instruction on Zen2 and later. I can't find the original comment or chat message from Mysticial where he confirmed faulting, but IIRC that's why I edited that fact into my answer – Manifesto

According to wikichip AMD added technology called predictive store forwarding and an instruction to disable it (PSFD) Is this not AMD-exclusive? I understand you obviously put a lot of work into this answer, but it needs to be exhaustive to be correct – Witchhunt

Based on the AMD manual, this is not an instruction but a CPUID bit. Besides, Intel mention it here and it does not look like an exclusive feature either because "PSFD is expected to be supported on all processors that support FSFP" and "FSFP [...] supported on certain Intel processors". – Chaim